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VLSI

The modern hardware-software world has formed through the massive integration of semiconductor devices. Today, as we face the end of Moore’s law and possibly the end of planar transistors under 20nm, this program adds perspective and direction to the knowledge required for the next decade and more.

chip

Market Drivers

  1. High degree of design abstraction level
  2. Technology Scaling – Smart Phones and Tablets
  3. Enhanced optimization techniques required to enable the design run at faster speed and occupy smaller area
  4. Implementation of complex digital SoCs using state of the art tools working with highly advanced process nodes.
  5. Modern VLSI design requires a lot of circuit knowledge. Designers are required to design their circuits with the help of EDA tools.
  6. Increased complexity and performance of systems on chip e.g. higher CPU performance, higher multimedia performance for wireless chips, etc.
  7. Faster time to market requires seamless and predictable PD flows with high sign off QoR to ensure high yield in deep submicron process nodes (28nm and beyond).
jobs

Job Proficiencies:

  1. Architecture concepts and trade-offs
  2. Strong fundamentals in Digital Design and CMOS concepts.
  3. Synthesis, DFT, Physical Design, Power-Aware, and Formal Verification flow
  4. Sound knowledge in clock and timing constraints
  5. Knowledge in timing closure
  6. Strong PERL and Tcl scripting skills
  7. Set up timing constraints and evaluate STA timing reports and drive closing timing effort at the block and chip level
objectives

Program Educational Objectives

  • Understand the complexities and design methodologies of VLSI/nanometer scale IC and ASIC design methodologies.
  • Apply advanced technologies in the fields of VLSI design along with the fundamental concepts.
  • Use techniques, skills, modern Electronic Design Automation(EDA) tools, software and equipment necessary to evaluate and analyze the systems in VLSI design environments.
  • Facilitatethe students using industry standard EDA tools and adopt sign-off design methodology for realizing complex VLSI systems for a given specification
outcome

Program Learning Outcomes

  • Apply advanced level knowledge, techniques, skills and modern tools of VLSI Design.
  • Understand the complexities and design methodologies of current and advanced IC design technologies.
  • Identify, formulate, and solve VLSI design problems using advanced level manufacturing techniques.
  • Able to plan, conduct an organized and systematic study on significant research topic within the field of VLSI and its allied field.

Location

Program Design

Year 1: Course work
Year 2: Internship/Project

Seminar

There shall be a technical seminar presentation on current & new development in Digital VLSI Design during II year.

Internship/Master’s Project Phase

Students will get opportunity to work with the industry as Interns during their project period to get real time experience.

Students will be required to take up a PG Project Work and submit their PG Project Report/Dissertation, after taking up a topic approved by the Project Review Committee (PRC).

The course focuses on performance metrics of processor and system architectures. It helps you to understand the impact of architectural elements on processor/system performance. It also teaches how to apply trends/trade-offs in modern architectural practice to Systems.

Course Objectives:

  1. Analyze and evaluate the performance metrics of processor and system architectures
  2. Understand the impact of architectural elements on processor/system performance
  3.  Apply trends/tradeoffs in modern architectural practice to Systems

Learning Outcomes:

  1. Applying the principles of hardware & software organization for performance/efficiency as applied to various systems
  2. Analyze computer systems for performance, efficiency and economics in target applications and optimize/resolve bottlenecks
  3. Articulate design choices in the optimization of computer systems
  4. Create/design optimal implementations of computer systems to meet specifications

The course deals with the study of IC physical design flow, challenges, and trends in VLSI back end flow. It helps you to understand the importance of logical & physical libraries. It covers concepts of floor planning, placement, clock tree synthesis & routing. It will help you to perform the complete back end flow using EDA tools.

Course Objectives:

  • To learn how to set the logic data setup, Physical data setup & generation of the net list
  •  To learn importance of timing constraints, Technology files
  •  Understand and apply the following concepts of
    •  Floor planning
    •  The Placement for Standard cells & macros
    •  The Clock Tree Synthesis
    •  Routing
    •  Sign off
  •  To create, optimize and deliver and SOC physical design

Learning Outcomes:

  1. Understand overall physical design and integration of an SOC
  2. Understand and apply cell libraries to physical design
  3. Create, optimize and deliver an SOC physical design by applying the following concepts and using the industry standard tools:
    • The timing constraints, synthesis & Generating Net list
    • The Floor plan with different shapes to reduce congestion &power consumption
    • The power network Synthesis
    • The PG Planning- Rings(core), Rings (I/O) Rings (around macros) & stripes
    • The Placement of standard cells & Macros
    • CTS
    • Congestion during Routing of the design
    • Parasitic extraction and STA
    • DRC & LVS
    • Formal verification and gate level simulation
The course helps you understand fundamental metrics used for quantitative evaluation of a design. It focuses on basics of MOS transistors and CMOS technology, combinational and sequential schemes, principles of design of digital units, modules of memory and other arithmetic circuits.It also helps you develop skills to design different memory elements and building blocks in digital circuits using Verilog language.

Course Objectives:

  1. Understand fundamental metrics used for quantitative evaluation of a design
  2. Learn the basics of MOS transistors and CMOS technology, combinational and sequential schemes, principles of design of digital units, modules of memory and other arithmetic circuits
  3. Apply the concepts of high level digital design using Verilog Hardware Description Language
  4. Understand the principles of design, analysis and simulation of digital circuits
  5. Design different memory elements and building blocks in Digital circuits
  6. Understand the concepts of timing issues in digital design

Learning Outcomes:

  1. Understand the principles of Logic design and digital architectural subsystems for VLSI
  2. Design Digital Functional units and memory units
  3. Design digital architectural subsystems for VLSI using Verilog HDL
  4. Analyze the RTL design and verify its functionality using basic Verilog test benches
  5. Design VLSI architectural, basic test benches and generating coverage reports for the RTL design and verify the functionality of the design through Simulation and waveform generation
  6. Perform Batch & GUI based Compilation & Simulation
  7. Generate Coverage metrics, SAIF files, UCLI files and perform gate level simulation

The course helps you learn various verification techniques. It helps you to write efficient test environment using System Verilog – assertions, randomized & constraint randomized test cases, interfaces, and coverage metrics. It also covers layered test bench architecture.

Course Objectives:

  1. Learn variousverification techniques.
  2. Learn the principles of verification, and use of SystemVerilog for verification
  3. Use System Verilog for efficient verification

Learning Outcomes:

  1. Understand the principles of verification and different test bench architectures used for verification
  2. ApplyOOPS concepts in System Verilog
  3. Build basic verification environment using System Verilog
  4. Generate random stimulus and track functional coverage using SV
  5. Perform constrain driven verification, assertion based verification and coverage driven verification using System Verilog
  6. Apply the concept of Layered test bench architecture and its components
Linux programming & scripting languages are lifeline of VLSI industry. The course helps you to gain expertise in using Linux as an OS & scripting languages like Perl and Python. This in turn, will help you to automate different processes in ASIC flow.

Course Objectives:

  1. Study scripting languages such as PERL, TCL/TK , Python and BASH for the automation of processes
  2.  Creation of programs in the Linux environment
  3. Use of scripting languages in ASIC design flow

Learning Outcomes:

  1. Create and run scripts using Perl / TCL / Python in ASIC design flow
  2. Use Linux environment and write programs for automation of scripts in VLSI tool design flow

The course helps you learn the fundamentals of ARM SoC architecture and its programming. It also explains the importance & usage of ARM architecture for system development. You will be able to program peripherals to interface with ARM7 architecture using embedded C.

Course Objectives:

  1. Learn the fundamentals of ARM SoC architecture and programming.
  2. Use of ARM architecture for system development
  3. Learn the art of connecting peripherals on ARM7 and programming using Embedded C.

Learning Outcomes:

  1. Apply the concepts ofARM architecture and memory hierarchy
  2. Learn the importance of cache memory in ARM processors
  3. Apply the concepts of AMBA architecture and ARM debug architecture
  4. Interface and program IO ports
  5. Implement I2C, SPI protocols on ARM7 microcontroller.
The course helps you learn the components of digital design & advanced concepts in synthesis process. It helps you to perform the complete synthesis process by setting the environment & synthesis constraints, generating the Netlist& analyzing the reports.

Course Objectives:

  1.  Understand the components of digital design & advanced concepts in synthesis process
  2.  Learn the art of selecting a technology, and setting the libraries, & design constraints
  3.  Analyze reports with respect to design on Area, Timing & Power

Learning Outcomes:

  1.  Set constraints, validate the results and analyze the reports
  2.  Synthesize the design based on Area and Timing priority
  3.  Perform critical path synthesis
  4.  Perform timing analysis on the synthesized netlist
  5.  Verify the functional equivalence of the synthesized netlist Vs RTL

The course helps you learn architectural elements, performance metrics and system architecture with primary focus on interfaces and protocols. You will be able to design protocols & interfaces using Verilog and verify using System Verilog. It also covers fundamentals of UVM for efficient test environment.

Course Objectives:

  1. Learn architectural elements, performance metrics and system architecture of computer systems
  2. Learn the concepts of verification components, test bench structure and Transaction-Level Modeling (TLM)
  3. Perform system-level verification with Universal Verification Methodology (UVM).
  4. Use of features and capabilities of the UVM class library for SystemVerilog.

Learning Outcomes:

  1. Learn the application of various protocol and interfaces
  2. Build and manage stimulus sequencers, drivers and monitors
  3. Build reusable verification components and environment using UVM
  4. Create reusable stimulus sequences, including for multi-layer protocols
  5. Create and manage configurable environments including agents, scoreboards, TLM ports and functional coverage objects
The course helps you understand the basic principles and methods of FPGA prototyping. It deals with programmable device architectures, their design and test methodologies. Some of the important topics included in the course are Verilog HDL based design and simulation, design realization on an FPGA, FPGA configuration, programming, testing and debugging.

Course Objectives:

  1.  Learn the basic principles and methods of FPGA prototyping.
  2.  Apply Programmable Device Architectures, Design them and learn test methodologies
  3.  Designand simulate using Verilog HDL
  4.  Design realization, configure, test and debugthe functionalities on FPGA board

Learning Outcomes:

  1.  Understand the principles of FPGA Design
  2.  Map an IP block and verify with an FPGA based system
  3.  Design, prototype and debug functionalities on FPGA board
The course helps you learn the concepts and techniques of testing. It covers test economy, analysis of different types of faults, circuit defects, fault modeling and simulation, automatic test pattern generation. It also covers BIST, MBIST & test point insertion techniques.

Course Objectives:

  1. Learn the concepts and techniques of VLSI design verification and testing
  2.  Understand the application of test economy, analyze different types of faults, &defects
  3.  Implement fault modeling and perform simulation & automatic Test Pattern Generation
  4.  Apply scan and boundary scan architectures & BIST architectures
  5.  Apply the concepts of memory testing

Learning Outcomes:

  1.  Learn the importance of testing, concepts of testability measures, scan cells and scan architectures, concepts of fault simulation and pattern generation
  2.  Apply test constraints, perform scan insertion and generate technology mapped netlist , scan ready netlist and scan stitched netlist
  3.  Perform pattern generation and get maximum coverage
  4.  Analyze different types of faults and reports at various levels of DFT flow
  5.  Build scan architectures and get the test coverage number
  6.  Perform fault simulation
  7.  Design & build BIST, JTAG and Memory Testing
The course helps youunderstand the design flow of SoC. It also helps you learn the art of integration of different IPs, and to understand the importance of different industry standard protocols & their applications.

Course Objectives:

  1. Understand the complexities of integrating different IPs on to a single chip
  2.  Learn the design flow of systems on chip
  3.  Apply architectural principles to build SoC
  4.  Understand the role & importance of different protocols in designing an SoC

Learning Outcomes:

  1.  Apply the fundamental concepts of SoC Design to build a specific SoC
  2.  Design the architectures of industry standard protocols while integrating different IPs inside an SoC
  3.  Apply the Verilog design techniques & design an efficient SoC

The course helps you learn CMOS low power techniques. It helps you to understand the effects of CMOS dynamic & static power consumptions and ways to optimize them. You will be able to design efficient power architectures using UPF.

Course Objectives:

  1. Learn CMOS low power techniques
  2. Understand the effect of CMOS dynamic & static power consumptions
  3. Design the power architecture using UPF

Learning Outcomes:

  1. Understand principles of design, analysis, modeling and optimization of low power IC design to reduce switching and leakage power
  2. Apply various approaches to estimate power consumption
  3. Model and use contemporary low power design techniques for optimization
  4. Design the power intent for a hierarchical design
  5. Perform muti-voltage simulations & static checks using MVSIM & MVRC respectively

The course deals with the design of standard cell libraries right from schematics to standard views. It covers schematics & layouts, characterization, parasitic extraction & generating final library in .DB format.

Course Objectives:

  1. Draw the schematic &layouts for a given Boolean equations
  2. Simulate the schematic design
  3. Understand DRC & LVS rules and debug DRC & LVS violations
  4. Learn Post layout simulation
  5. Understand the importance and application of parasitic extraction & Characterization
  6. Understand the static and dynamic properties of MOS circuits, propagation delays and modeling of transistors
  7. Build a digital CMOS standard cell library and then using it to build a digital system ASIC.

Learning Outcomes:

  1. Convert Boolean equation to transistor level design
  2. Simulate schematic design
  3. Verify the functionality for a given design
  4. Design a layout using Euler’s Path
  5. Debug DRC & LVS violations and extract parasitic
  6. Perform post layout design and characterization
  7. Analyze different output formats from different tools
  8. LIB format to .DB format
  9. Generate standard views for export of standard cells

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