This course is designed for aspirants looking for a stable career in VLSI Physical Design. It deals with the study of IC physical design flow and challenges in VLSI Back End Flow. Participants will learn from netlist to GDS2 by setting the Logical & Physical libraries, constraints & generate synthesized net list; learn importance of timing constraints, Technology files, understand and apply the concepts to do Floor planning, Placement for Standard cells & Macros, Clock Tree Synthesis & Optimization, Routing & Sign off to create optimized netlist.

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• Learn the physical design concepts and the challenges in the back end flow.
• Understand and apply the following concepts:
  • Floor planning
  • The Placement for Standard cells & macros
  • The Clock Tree Synthesis
  • Routing
  • Sign off

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• Perform the complete physical design flow by applying the following the concepts and using the industry standard tools:
• Setting the environment, logical & physical libraries and technology files
• The timing constraints, synthesis & Generating Net list
• The Floor plan with different shapes to reduce congestion & Power consumption
• The Power network Synthesis
• The PG Planning- Rings(core), Rings (I/O) Rings (around macros) & stripes
• The Placement of standard cells & Macros
• Clock Tree Synthesis and Routing

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• Physical design concepts and setup
• Design constraints & timing constraints
• Design & power planning
• Global placement, CTS, STA and Routing concepts

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Tools used:

IC Compiler

Pre-requisites:

CMOS, digital design and synthesis concepts

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Target Audience:

BE / B.Tech / ME / M.Tech (Electronics and related branches), Working professionals, Academic Faculty

Location:

Classes can be conducted physically / virtually. Depending upon the students count, the classes can be conducted at Seer Office or at other location physically. Online meetings software will be used for virtual classes.

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