This certification helps you develop the skill sets that the industry demands. You will develop skills in system design, RTL design using Verilog, writing test benches in Verilog and development of basic / complex building blocks. You will be able to generate synthesised Netlist consisting of equivalent cells with their interconnection. It will conclude with an industry oriented project work.
This certification helps you develop skills required to become a verification engineers. It covers writing basic test benches and to develop complete verification environment using System Verilog. You will also get exposure to Universal Verification Methodology (UVM). The course will conclude with an industry oriented project work.
This course is designed for aspirants looking for a stable career in VLSI Physical Design. It deals with the study of IC physical design flow and challenges in VLSI Back End Flow. Participants will learn from netlist to GDS2 by setting the Logical & Physical libraries, constraints & generate synthesized net list; learn importance of timing constraints, Technology files, understand and apply the concepts to do Floor planning, Placement for Standard cells & Macros, Clock Tree Synthesis & Optimization, Routing & Sign off to create optimized netlist.