This certification helps you develop skills required to become a verification engineers. It covers writing basic test benches and to develop complete verification environment using System Verilog. You will also get exposure to Universal Verification Methodology (UVM). The course will conclude with an industry oriented project work.
Write good verification environment using System Verilog
Verify the design to ensure 100% coverage
Write directed & randomized test cases
Write assertions & generate constraint random test cases to hit the corner cases
BE / B.Tech / ME / M.Tech (Electronics and related branches), working professionals, academic Faculty
Classes can be conducted physically / virtually. Depending upon the students count, the classes can be conducted at Seer Office or at other location physically. Online meetings software will be used for virtual classes.