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Advanced Digital Logic Verification

This certification helps you develop skills required to become a verification engineers. It covers writing basic test benches and to develop complete verification environment using System Verilog. You will also get exposure to Universal Verification Methodology (UVM). The course will conclude with an industry oriented project work.

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Objectives

  • Write good verification environment using System Verilog
  • Verify the design to ensure 100% coverage
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Learning Outcomes

  • Write directed & randomized test cases
  • Write assertions & generate constraint random test cases to hit the corner cases
  • Design a layered test bench architecture
  • Generate & analyse functional coverage, code coverage, line coverage & FSM coverage
  • Design a basic test environment using UVM

Tools Used

GTKWave, VCS

Prerequisites

Digital Design Fundamentals,Verilog-HDL
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High Level Course Content

  • Verification concepts
  • System Verilog language construct – randomization & constraint randomization, interfaces, clocking blocks, assertions, cover points
  • Layered testbench architecture – Checker, sequencer, generator, mailbox
  • Basic UVM constructs & classes
  • Verification environment for protocol using UVM

Target Audience:

BE / B.Tech / ME / M.Tech (Electronics and related branches), working professionals, academic Faculty

Location:

Classes can be conducted physically / virtually. Depending upon the students count, the classes can be conducted at Seer Office or at other location physically. Online meetings software will be used for virtual classes.

For more information, please contact

programs@seerakademi.com

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