This course is designed for aspirants looking for a stable career in VLSI Physical Design. It deals with the study of IC physical design flow and challenges in VLSI Back End Flow. Participants will learn from netlist to GDS2 by setting the Logical & Physical libraries, constraints & generate synthesized net list; learn importance of timing constraints, Technology files, understand and apply the concepts to do Floor planning, Placement for Standard cells & Macros, Clock Tree Synthesis & Optimization, Routing & Sign off to create optimized netlist.
Learn the physical design concepts and the challenges in the back end flow.
Understand and apply the following concepts:
The Placement for Standard cells & macros
The Clock Tree Synthesis
Perform the complete physical design flow by applying the following the concepts and using the industry standard tools:
Setting the environment, logical & physical libraries and technology files
The timing constraints, synthesis & Generating Net list
The Floor plan with different shapes to reduce congestion & Power consumption
BE / B.Tech / ME / M.Tech (Electronics and related branches), Working professionals, Academic Faculty
Classes can be conducted physically / virtually. Depending on the students count, the classes will be conducted at Seer Office, Hyderabad or at other location physically. Online meeting software will be used for virtual classes.